An analog-to-digital converter (ADC) maps a continuous voltage onto a finite set of integer levels. It does so in two stages. Sampling discretises the signal in time; quantisation discretises it in amplitude. The output is a sequence of $N$-bit numbers that downstream digital systems can store, transmit, and process without further loss of fidelity. This page develops both stages, derives the resolution and noise limits they impose, and examines the successive-approximation register (SAR) architecture used in most biomedical instrumentation.
In a biomedical instrument the signal traverses several analog stages before any digital processing is possible. An electrode delivers a biopotential of a few millivolts. An instrumentation amplifier raises that signal to a level on the order of volts. An anti-alias filter then limits its bandwidth to below half of the intended sample rate. At every point along this chain the voltage is continuous in both time and amplitude.
The ADC is the final analog block. It samples the conditioned voltage at regular intervals and assigns each sample an integer code. Once the signal is a sequence of integers, all subsequent processing (filtering, peak detection, heart-rate estimation, logging, transmission) is performed in software on a microcontroller and adds no further analog distortion.
The comparator and Schmitt trigger described earlier in this week are one-bit decision elements. An ADC generalises the same operation to $N$ bits. A successive-approximation ADC reuses a single comparator over $N$ clock cycles. A flash ADC instead places $2^N - 1$ comparators in parallel and resolves all bits within one clock edge. The trade-off is conversion latency against silicon area and power consumption.
A sampling clock at rate $f_s$ defines the instants at which the converter inspects its input. Voltages between successive clock edges are discarded. The output is a discrete-time sequence $x[n] = v(n / f_s)$, with one sample per period $T_s = 1/f_s$.
The Nyquist sampling theorem states that a band-limited signal of highest frequency $f_\mathrm{in}$ can be recovered exactly from its samples if and only if $f_s > 2 f_\mathrm{in}$. When $f_s \le 2 f_\mathrm{in}$ the same sample sequence is consistent with at least one lower-frequency signal as well as the original, and the converter cannot distinguish the two. The lower-frequency replica is called an alias. It is what subsequent digital processing receives.
In the figure on the right, raising $f_\mathrm{in}$ above the dashed Nyquist marker at $f_s/2$ folds the sampled trace onto a lower-frequency replica. In practice an anti-alias filter precedes every ADC and removes spectral content above $f_s/2$ to prevent this in advance.
Sampling discretises time. Quantisation discretises amplitude. An $N$-bit converter with full-scale range $V_\mathrm{ref}$ divides that range into $2^N$ equally spaced levels. Each sample is rounded to the nearest level and reported as the integer index of that level. The voltage spacing between adjacent levels is the least-significant bit (LSB):
$$ \mathrm{LSB} = \frac{V_\mathrm{ref}}{2^N}. $$
The rounding error is bounded by $\pm \mathrm{LSB}/2$ and is well approximated by an additive uniform noise source. For a full-scale sinusoid the resulting signal-to-quantisation-noise ratio is
$$ \mathrm{SQNR} \approx 6.02\,N + 1.76\;\mathrm{dB}, $$
so each additional bit improves the SQNR by approximately $6\,\mathrm{dB}$. A $3$-bit converter produces a visibly stepped output. Eight bits is sufficient for control signals and coarse biomedical recording. Twelve bits is the standard resolution for ECG and EMG. Sixteen to twenty-four bits are reserved for audio and precision measurement.
In the figure on the right, the bit-depth slider varies $N$. The lower trace shows the residual error $v(t) - v_q(t)$ between the analog input and its quantised version on the same time axis.
A successive-approximation register (SAR) ADC consists of a single comparator, an internal digital-to-analog converter (DAC), and an $N$-bit register. The converter resolves a held input voltage by binary search of the reference range, processing one bit per clock cycle starting from the most-significant bit.
On each cycle the DAC produces a trial voltage $V_\mathrm{DAC}$ and the comparator returns a single binary decision:
After $N$ cycles all bits have been resolved and the register holds the final code. The conversion time is fixed at $N$ clock periods regardless of input value. SAR converters are therefore deterministic in latency and dissipate energy only when their internal switches change state.
In the figure on the right, varying $V_\mathrm{in}$ shows the convergence of the algorithm. Each step halves the remaining uncertainty until that uncertainty equals one LSB.
The figure on the right shows the canonical SAR ADC. The held input $V_\mathrm{in}$ drives the non-inverting input of a clocked comparator. The internal DAC drives the inverting input. A control register stores the bits resolved so far and presents them to the DAC. A clock advances the algorithm by one bit per active edge.
The DAC is typically implemented as a binary-weighted capacitor array because capacitors carry no static current and match well in modern CMOS. The comparator is a clocked latch so that its output is valid by the next rising edge. The control register is a simple shift-and-test state machine that maintains the partial code.
The reference voltage $V_\mathrm{ref}$ is held constant throughout the conversion. It sets the converter's full-scale range, so the trial voltage at cycle $k$ is $V_\mathrm{DAC}(k) = (\text{code}_k / 2^N)\,V_\mathrm{ref}$. Only the code changes from one cycle to the next. $V_\mathrm{ref}$ does not.
The capacitors carry binary-weighted shares of the full scale: $V_\mathrm{ref}/2$, $V_\mathrm{ref}/4$, $V_\mathrm{ref}/8$, and so on down to $V_\mathrm{ref}/2^N$. A switch connects each capacitor to either $V_\mathrm{ref}$ or ground according to the current value of its bit. Capacitors whose bits equal $1$ sum their fractions onto the comparator's inverting input. The total of that sum is $V_\mathrm{DAC}$. The comparator therefore tests, on every cycle, whether $V_\mathrm{in}$ lies above or below the present $V_\mathrm{DAC}$. The result becomes the new bit, and the next cycle adjusts the capacitor pattern accordingly.
The complete loop comprises one comparator, one DAC, $N$ clock cycles, and one register. Power, area, and design complexity are all modest. SAR ADCs are therefore the dominant architecture in biomedical front-ends, spanning from $8$-bit pulse oximeters to $24$-bit electroencephalographs.
Every analog stage adds noise to the signals that pass through it. When a signal traverses multiple stages (cable, amplifier, filter, transmitter), the noise contributions add and the signal-to-noise ratio degrades monotonically with the number of stages.
A digital signal admits only two valid states. Provided the noise on a wire remains below the threshold gap separating $0$ from $1$, any subsequent comparator can regenerate a clean copy. The ADC marks the transition into this regime. Once a voltage has been mapped to a bit pattern, that pattern can be transmitted, stored, copied, and processed indefinitely without further degradation.
In the figure on the right, the same input is processed by three identical noisy stages in two configurations. The upper trace is fully analog. The noise band widens at each stage. The lower trace is digitised after the first stage and the bit pattern is regenerated at every subsequent stage. Its noise band remains bounded by half of an LSB.
As the per-stage noise is increased, the analog signal sinks into its noise floor while the digital signal remains intact, up to the point at which the noise exceeds the bit-decision threshold and digital errors appear. The transition between graceful analog degradation and abrupt digital failure is itself useful: it tells the system designer unambiguously when the link has stopped functioning.